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In this paper, we introduce a new method for building covert channels which
uses the DRAM power consumption estimates given by the processor's internal
power measuring registers.
We evaluate in detail the performance of the covert channel with respect to throughput,
error rate, and robustness against application interference.

We show how to combine DRAM and CPU power consumption states to achieve higher transmission
rates. Using this method, our channel implementation improves upon similar proposals,
with respect to bandwidth and robustness against application interference.
Using more complex encoding and decoding techniques, higher transmission rates with
lower error rates may be achieved.

A simple countermeasure to these covert channels is to prohibit applications from reading
the power consumption registers, but this may be to restrictive. Another possible solution would be
to allow applications to read the consumption only at low rates. However, further research is
needed to find which sampling rates are secure but also give useful information to applications.

For future work, it is interesting to derive a capacity bound for the DRAM-based covert channel
as Miedl and Thiele~\cite{miedl2018security} consider for the CPU-based one.
It would also be interesting to consider error correction codes to lower the error rates.
Another possible extension of this work would be to compare the bandwidth and error rates
of the channel when running in different environments.
